Programmable Logic Devices (PLDs) are Integrated Circuits (ICs) that are used to implement digital logic operations according to user configurable input. Example PLDs include Complex Programmable Logic Devices (CPLDs) and Field Programmable Gate Arrays (FPGAs). CPLDs often include several function blocks that are based on programmable logic array (PLA) architecture with sum-of-products logic. A configurable interconnect matrix transmits signals between the function blocks.
An example FPGA includes an array of configurable logic blocks (CLBs) and a ring or columns of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure (routing resources). The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration bitstream may be read from an external memory, conventionally an external integrated circuit memory EEPROM, EPROM, PROM, and the like, though other types of memory may be used. The collective states of the individual memory cells then determine the function of the FPGA. A specific type of FPGA uses a look-up-table (LUT)-based CLB. The configuration memory provides input values to a number of multiplexers controlled by inputs to the CLB.
A conventional design process for an integrated circuit, such as an ASIC or an FPGA begins with the creation of the design. The design specifies the function of a circuit design at a schematic or logic level and may be represented using various programmable languages (e.g., VHDL, ABEL or Verilog) or schematic capture programs. The design is synthesized to produce a logical network list (“netlist”) supported by the target integrated circuit device. The synthesized design is mapped onto primitive components within the target device (e.g., programmable logic blocks of an FPGA). Placement of the components of the synthesized and mapped design is then performed for the target device. Interconnects (e.g., signal conductors) are routed within the target device for the placed components. Place-and-route procedures sometimes involve optimizations of a design's timing, power consumption, area and any combination thereof. In some instances, timing-based estimations of the design are also provided.
PLD technology is rapidly advancing on many different fronts. One such area of advancement involves increases in speed and density of the resources on a PLD. Much advancement can be credited to improvements in the underlying semiconductor devices forming the various PLD components. For example, transistor technology has seen significant improvements due to smaller transistor sizes. These and other changes, however, are not without their costs.
As the technology evolves, the transistors, and similar IC components, may become increasingly sensitive to process variations. Such increased sensitivity can be attributed to a number of factors including smaller transistors sizes (e.g., width and length), thinner gate oxide, low levels of dopant impurities in the channel, proximity of transistors to other components or well boundaries, and lithographic resolution. Moreover, as device speeds increase, they often become more susceptible to timing variations. Process variations may also result in performance variations between similar interconnects. For instance, variations in metal wire width and height variation, and inter-layer dielectric thickness variation, among other factors, may affect the performance of interconnections. Moreover, a particular interconnection's variation may have a dependency on its location and layout. This is partially due to the fact that the same amount of variation may result in disparate impacts on parts exhibiting different timing requirements.
What is needed is a method by which deviations from ideal process performance in a design configuration in a programmable logic device can be compensated for. The method should derive its compensation data from the performance data of the target programmable logic device and from the configuration data of the design configuration.